Efficient Timing Element Design Featuring Low Power Vlsi Applications

In this paper, we propose a novel Low-Power Dual dynamic node and edge triggered (DDNET) flip flop for Featuring Efficient low power applications. Several art of design techniques have been proposed to eliminate large capacitance in the precharge node of the conventional flip-flop, which drives separately by output pull-up, and pull down transistors. Though the pioneer designs which consumes much power and it has been overcome by our special handing techniques. The major aim of this work is to optimize the static current and total power dissipation of the flip-flop, which has designed through DDNET flip flop design. The proposed designs which outperforms the existing designs in terms of reduction of total power Dissipation and static current. The proposed DDNET flip flop design provides a power reduction up to 7.1% and 6.4% compared to the conventional flip-flops at 20% and 35% data activities, respectively. The performance of proposed timing element design is analyzed by simulating the element (Flip flop) circuit at 180nm CMOS process technology. The simulation evaluation outcome shows that, the proposed design (DDNET) achieves less number of transistor count up to 30-40% than the conventional method, In addition the Improvement of Power Energy Product (PEP) up to 30-34% and 5-10% reduction in static current Compared to the dual dynamic node hybrid flip-flop. Futher, In this work design and simulation of a 5 MHz, divide-by-2 frequency divider based upon DDNET logic flip-flops in 180 nm CMOS technology are presented. The performance improvements specify that the proposed Designs are appropriate for modern high-performance designs where power dissipation is of major Concern. Keyword-DDNET, flip flops, static current, low power, frequency divider.